London - The rebranding of IBM's servers as the eSeries is much more than a name change, according to VP of enterprise servers Richard Lechner. It speaks volumes about what IBM's long-term plans for the server product are, as it continues to seek cost savings by sharing components and the cross-fertilization of technologies between different platforms.
Chairman Louis Gerstner's plan is to shift away from relying on margins from the server business to deliver the bottom line -- and therefore away from proprietary systems and operating systems -- and towards middleware, services and technology.
Ultimately, we expect IBM to focus on selling single eSeries server platforms with shared components, system utilities and software (vis a vis Linux) in specific operating system and application packages. When? "Soon," said Lechner.
The forthcoming introduction of IBM's Power4 systems, the migration of technologies such as the mainframe LPAR logical partitioning onto other servers, and the proliferation of Linux (now also available on AS/400, or iSeries) are clear indications of this trend.
IBM will begin early shipments of its Power4 Regatta Aix servers in the fourth quarter, with general delivery scheduled for the beginning of 2002. The first systems will run at 1GHz, with a crank to 1.3GHz due during 2002.
The eight-way multichip modules -- each Power4 board has two chips packaged in 32-way SMP units. They use a quasi-NUMA UMA (unified memory architecture) memory model with an L3 cache that is shared (for local cache miss look up) and doesn't break the SMP programming model as other ccNUMA architectures do, having a very low latency.
IBM claims at least 32-way of the 32-way nodes can be clustered using its SP Colony switch with a latency of 9ms (microsecond). An AIX image runs on each. Each individual 32-way node can also be partitioned into smaller systems with Lpar logical partitioning, or be configured as smaller clusters with Colony. IBM has also talked about directly connecting two or three of the nodes together without a switch.
The next-generation Federation switch, with a much smaller latency, will follow, plus support for other interconnects -- including Ethernet, GigabitEthernet and third-party products, such as the Miracom switch, which is developing support for AIX.
In the end, it's not about adding more throughput to the system; it's about offering customers different levels of interconnection speed, IBM said.
Currently, there are many hardware dependencies that preclude a customer choosing a system independently of the switch. As PSSP (parallel system support program) and other features are supported directly in the AIX kernel, so they'll be able to choose what form (and speed) of interconnect is most suitable for their application load.
A major 5.2 release of AIX 5L next June will see more of the clustering and system utilities integrated directly into AIX.
Regatta, then, is effectively an SP system, or Bleu Hammer (IBM's IAX clustering technology), plus a switch.
At the high-end, the HPC high-performance computing group has its own Power4 roadmap, which includes a new breed of 'rack and stack' servers and traditional SP systems, with huge memory and go-faster CPUs.
Linux will become important over time, but the notion of running Linux on a 32-way system, or supporting 32 Linux images, simply doesn't fly yet, IBM admits. Its Linux application execution environment for AIX effectively recompiles Linux application into AIX. Long-term, Linux is still the development API for AIX and it will encourage AIX ISVs to migrate.
IBM said current G7 mainframe servers that run at 1GHz will get a speed crank next year to 1.3GHz. But the next step change in functionality (G8) won't arrive until the fruits of what IBM calls Project Galileo are productized, which won't be for another two to three years.
This will result in taking the Intelligent Resource Director, which combines workload manager, logical partitioning and parallel Sysplex clustering, and allowing four maximum configurations to run under the control of one operating system image -- unlike the one image each currently requires). Parallel Sysplex today enables 32 16-way systems to be clustered together.
The new carbon nano chip process -- which further extends the life of current process design by getting electrons to line up in specific fashion to offer better processing -- won't be implemented for another three to five years.
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